I am back. Back on my blog and back to work. I like to say engaged vs idle instead of out of work and back to work, so I am back to fully engaged. About two months ago my network paid off and one of my colleagues and good friends connected me to an ASIC company that wanted to create an FPGA emulation of their next generation offering. A big IC of 20+ million gates need to be partitioned into a number of the largest and fastest FPGA’s that Xilinx can provide. So, I am back in the ASIC world while still in the FPGA world. Great opportunity to bring old experience to bear and gain new experience in the growing field of FPGA emulation. I am getting exposed and re-exposed to processes of version control, cross-functional teams, systemVerilog, a suite of ASIC and FPGA verification and synthesis tools, etc. I am also working most of the time back in an office, cubicle, environment. More on that later. So for those in my network that were pulling for me to get a new assignment, thanks for your support and keep a look out for new work as this assignment won’t last forever.